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ics for communications octal transceiver for dasl compatible interfaces octat-p peb 2096 version 2.1 addendum 05.98 to the data sheet 01.96 ds 1
edition 05.98 this edition was realized using the software system framemaker a . published by siemens ag, bereich halbleiter, marketing- kommunikation, balanstra?e 73, 81541 mnchen ? siemens ag 1996. all rights reserved. attention please! as far as patents or other rights of third parties are concerned, liability is only assumed for components, not for application s, pro- cesses and circuits implemented within components or assemblies. the information describes the type of component and shall not be considered as assured characteristics. terms of delivery and rights to change design reserved. for questions on technology, delivery and prices please contact the semiconductor group offices in germany or the siemens com- panies and representatives worldwide (see address list). due to technical requirements components may contain dangerous substances. for information on the types in question please con- tact your nearest siemens office, semiconductor group. siemens ag is an approved cecc manufacturer. packing please use the recycling operators known to you. we can also help you C get in touch with your nearest sales office. by agreeme nt we will take packing material back, if it is sorted. you must bear the costs of transport. for packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for an y costs incurred. components used in life-support devices or systems must be expressly authorized for such purpose! critical components 1 of the semiconductor group of siemens ag, may only be used in life-support devices or systems 2 with the express written approval of the semiconductor group of siemens ag. 1 a critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sust ain human life. if they fail, it is reasonable to assume that the health of the user may be endangered. peb 2096 revision history: current version: 05.98 previous version: data sheet 01.96 page (in version 01.96) page (in new version) subjects (major changes since last revision) 13 4 general principle of the dasl compatible interface 24 7 external circuitry for dasl compatible interface 27 7 loop 2 is no longer supported. 29 8 transmit delay of b- and d-channels 30 9 frame synchronization 31 10 the arbiter function of the d-channel handler is not supportet. 37 10 command / indicate channel 40 12 octat-p state diagram 47 16 configuration register non 17 mode register (new)
peb 2096 semiconductor group 3 05.98 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2.1 device architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2.2 interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2.2.1 general principle of the dasl compatible interface . . . . . . . . . . . . . . . . . . . .4 2.2.2 iom-2 system interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 2.2.3 jtag boundary scan test interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 2.3 individual functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 2.3.1 transceiver, analog connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 2.3.2 diagnostic functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 3 operational description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 3.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 3.2 clocking, reset and initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 3.3 push C pull sensing on pin du . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 3.4 transmit delay on dasl compatible interface with respect to iom ? -2 inter- face 8 3.5 dasl compatible frame synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3.5.1 synchronization with a short fsc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3.5.2 synchronization using ssync (for dect) . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3.6 d-channel handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 3.7 iom ? -2 interface monitor channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 3.8 command / indicate channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 3.9 activation and deactivation, state machine . . . . . . . . . . . . . . . . . . . . . . . . . .11 3.9.1 states description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 3.9.2 info structure on the dasl compatible interface . . . . . . . . . . . . . . . . . . . . .13 3.9.3 example of activation and deactivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 4 registers description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 4.1 identification register C (read) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 4.2 general configuration register C (write) . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 4.3 bit error register C (read) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 4.4 configuration register for dasl compatible line interfaces C (write) . . . . .16 4.5 test registers C (read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 4.6 mode register C (write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
semiconductor group 4 05.98 peb 2096 1 overview the octal transceiver for dasl compatible interfaces, octat-p, peb 2096, implements the two-wire dasl compatible interface used to link voice/data digital terminals to pbx subscriber lines. the octat-p is an optimized device for lt applications and can handle up to eight dasl compatible interfaces simultaneously. the octat-p is a cmos device offered in a p-mqfp-44 package. 2 functional description the peb 2096, octat-p, performs the layer-1 functions of the isdn basic access for eight dasl compatible interfaces at the lt side of the pbx. 2.1 device architecture the octat-p contains the following functional blocks: ? eight line transceivers for the dasl compatible interfaces ? one iom-2 interface ? frame structure converter between the iom-2 interface and the dasl compatible interfaces ? jtag boundary scan interface ? clocking, reset and initialization block 2.2 interfaces 2.2.1 general principle of the dasl compatible interface a frame transmitted by the exchange (lt) is received by the terminal equipment (te) after a given propagation delay ( t d ). refer to figure 1 . the terminal equipment waits a guard time of six bits ( t g = 15.6 m s) while the line clears. it then transmits a frame to the exchange. the exchange begins a transmission every 250 m s (known as the burst repetition period). however, the time between the reception of a frame from the te and the beginning of transmission of the next frame by the lt must be greater than the minimum guard time. communication between an lt and a pt (private termination) follows exactly the same procedure. note that the guard time in te is always defined with respect to the last d-bit.
peb 2096 semiconductor group 5 05.98 figure 1 dasl compatible interface frame structure within a burst, the data rate is 384 kbit/s. the 37-bit frame structure is as shown in figure 1 . the framing bit (lf) is always logical 1. the frame also contains the user channels (2b + d). it can readily be seen that in the 250 m s burst repetition period, 4 d bits, 16 b1 bits and 16 b2 bits are transferred in each direction. this results in an effective full duplex data rate of 16 kbit/s for the d channel and 64 kbit/s for each b channel. the octat-p scrambles b- and d-channel data on the dasl compatible interface in order to ensure that the downstream receiver gets enough pulses for a reliable clock extraction (flat continuous power density spectrum is provided) and no periodic patterns appear on the line. the scrambling polynomial is: x 9 + x 5 + 1. the coding technique used on the u interface is a ami code. a logical 0 corresponds to a neutral level, logical 1 are coded as alternate positive and negative pulses. lf b1 b2 8 1 8 8 8 b2 b1 timings: =burst repetition period =line delay =guard time = 250 t r d t t g m s s m = 13 = 15.6 m s maximum minimum (6 bits) g t t d r t d t 96.35 m s lf-framing bit lt te/pt t g > d 2 d 2
peb 2096 semiconductor group 6 05.98 see figure 2 . the ami coding includes always the data bits going on the dasl compatible interface in one direction. thus there is a separate ami coding unit for data downstream and one for data upstream. figure 2 ami coding on the dasl compatible interface 2.2.2 iom-2 system interface unchanged 2.2.3 jtag boundary scan test interface idcode the 32-bit identification register is serially read out via tdo. it contains the version number (4 bits), the device code (16 bits) and the manufacture code (11 bits). the lsb is fixed to 1. note: in the state test logic reset the code 0011 is loaded into the instruction code register. version device code manufacture code output 0xxx 0000 0000 0001 0100 0000 1000 001 1 --> tdo 0010 version 1.3 0011 version 2.1 binary values line signal from the octat 0 1 0 0 1 1 0
peb 2096 semiconductor group 7 05.98 2.3 individual functions 2.3.1 transceiver, analog connections figure 3 external circuitry for dasl compatible interface the peb 2096, octat-p, covers the electrical requirements of the dasl compatible interface for loop lengths depending on the used transformer and the cable quality: note: the actual values of the external resistors depend on the selected transformer. the resistor values in figures 3 are tbd. 2.3.2 diagnostic functions loop 2 is no longer supported. transformer cable loop length 4:1 awg 24 5.5 kfeet octat-p . . . . . 820 820 tbd (390) tbd (390) 100 nf 0.33 f 1 : 4 dasl line
peb 2096 semiconductor group 8 05.98 3 operational description 3.1 general all procedures required for data transmission over the dasl compatible interface are implemented. these comprise the dasl compatible interface frame synchronization, activation/deactivation procedure, and timing requirements such as bit rate and jitter. 3.2 clocking, reset and initialization unchanged 3.3 push C pull sensing on pin du unchanged 3.4 transmit delay on dasl compatible interface with respect to iom ? -2 interface the octat-p causes delays of b- and on d-channels with respect to the iom channel number. figure 4 shows this delay at a data rate of 2.048 mbit/s. . figure 4 transmit delay of b- and d-channels 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 125 s 250s u frame lt -> te data downstream channels fsc d d b1 b2 b1 b2 d d b1 b2 b1 b2
peb 2096 semiconductor group 9 05.98 3.5 dasl compatible frame synchronization there are two possibilities how to synchronize the dasl compatible frame to the iom-2 frame: with a short fsc or with ssync . 3.5.1 synchronization with a short fsc the short fsc pulse has a width of one dcl clock (in normal use the fsc is at least 2 dcl wide). the ssync input must be set to 1. the period of the short fsc pulses must be a multiple of 250 m s. the dasl compatible transmit frame starts in the iom channel 0 which follows the short fsc pulse. refer to figure 5 . figure 5 synchronization with a short fsc 3.5.2 synchronization using ssync (for dect) a zero pulse on the ssync input forces the octat-p to start a frame at the beginning of this iom frame. refer to figure 6 . figure 6 synchronization with ssync while using ssync for dasl compatible frame synchronization the short fsc signal is not allowed. if not used, the ssync input must be connected to v dd . fsc data downstream dasl channel n fsc data downstream dasl channel n ssync
peb 2096 semiconductor group 10 05.98 3.6 d-channel handling the arbiter function of the line card d-channel handler is not supportet. 3.7 iom ? -2 interface monitor channel unchanged 3.8 command / indicate channel the c/i channel is used for communication between the octat-p and a layer-2 device (or elic), to control and monitor layer-1 functions. the layer-2 device monitors the layer-1 indication continuously and indicates a change if a new code is found to be valid in two consecutive iom frames (double last look criterion). table 1 commands command (downstream) abbr. code remarks deactivate request dr 0000 reset res 0001 test mode 2 tm2 0010 transmission of pseudo-ternary pulses at 2 khz frequency test mode 1 tm1 0011 transmission of pseudo-ternary pulses at 192 khz frequency activate request ar 1000 1100 1010 transmission of info 2 or info 4. activate request local test loop arl 1001 transmission of info 2, switching of loop 1 (on dasl compatible interface) deactivate confirmation dc 1111 deactivation acknowledgment, quiescent state
peb 2096 semiconductor group 11 05.98 3.9 activation and deactivation, state machine 3.9.1 states description octat-p state machine enters two different kind of states: unconditional and conditional states, figure 7. table 2 indications indication (upstream) abbr. code remarks timing required (to activate iom-2) tim 0000 deactivated state, activation from the line not possible resynchronization (loss of framing) rsy 0100 receiver is not synchronous activate request ar 1000 info 1w received u only activation indication uai 0111 info 1 received synchronous receiver activate indication ai 1100 layer-1 fully activated deactivate indication di 1111 info 0 or dc received after deactivation request
peb 2096 semiconductor group 12 05.98 figure 7 octat-p state diagram itd10700 activated al i4 i3 dc arx,al arx,al dc i1 i4 uai synchronized arx dc i1 i2 rsy resynchron. unconditional transitions initiated by commands: external pins: arx = ar, arl rst res, tm1, tm2 pend.oct. ar i2 i1w dc arx deactivated di i0 i0 wait for dr di i0 i0 pend.deact. tim i0 i0 ind state cmd out in u dr fs dr fs fs fs dc dr dr fs i1w, arx dc dr dr dr arx tm2 tm1 * it tim test mode i dr tm1 tm2 reset tim i0 * res res dr rst dc i0 i xr i + corrupt frame *) r iom r iom fs : synchronized to received frame (fs = 1) fs : loss of synchronization (fs = 0) dasl state for one iom frame only
peb 2096 semiconductor group 13 05.98 conditional states deactivated this is the power down state of the physical protocol. the awake detection is active and the device will respond to any signal on the line (wake signal) by initiating activation. pending activation this state results from a request for activation of the line, either from the terminal (info 1w) or from the layer-2 device (ar or arl). info 2 is then transmitted and the octat-p waits for the responding info 1 from the remote device. synchronized upon receipt of info 1 the octat-p must synchronize itself to the signal (fs = 1). synchronization is achieved after the detection of at least 4 consecutive valid frames. this process takes at most 10 ms note: this state is a drop through state and appears for one iom frame before entering the state activated. activated the line is activated; the octat-p sends info 4 to the remote, the remote sends info 3 to the octat-p. resynchronization if the octat-p looses synchronization (fs = 0), for whatever reason, it will attempt to resynchronize. synchronization is lost after the detection of at least 4 consecutive invalid frames. entering this state it will output info 2. this is similar to the original synchronization procedure in the pending activation state (the indication given to layer 2 is different). however as before, recognition of a valid frame (fs = 1) leads to the synchronized state. refer to octat-p state diagram in figure 7 . 3.9.2 info structure on the dasl compatible interface signals controlling and indicating the internal state of all dasl compatible transceiver state machines are called infos. four different infos (info 0, 1w, 1/2 and 3/4) can be sent over the interface depending on the actual state (synchronized, activated, pending activation, test mode, deactivated, reset,...) of the connected transceivers. when the line is deactivated info 0 is exchanged by the transceivers at either end of the line. info 0 indicates that there is no signal on the line; in either direction.
peb 2096 semiconductor group 14 05.98 when the line is activated info 3 (in upstream direction) and info 4 (in downstream direction) are continually sent. info 3 and 4 contain the transmitted data (b1, b2, d). info 1w and 1/2 are used for initialization. the form of each info is shown in the following table: note: f = framing bit name direction description info 0 upstream downstream no signal on the line info 1w upstream asynchronous wake signal 2 khz burst rate f=1, b and d channels contain scrambled 1 info 1 upstream 4 khz burst rate f=1, b and d channels contain scrambled 1 info 2 downstream 4 khz burst rate f=1, b and d channels contain scrambled 1 info 3 upstream 4 khz burst rate f=1, b and d channels contain scrambled data info 4 downstream 4 khz burst rate f=1, b and d channels contain scrambled data
peb 2096 semiconductor group 15 05.98 3.9.3 example of activation and deactivation the activation and deactivation procedure between an octat-p and a dasl compatible terminal device is shown in figure 8 . it illustrates how the state machines of the respective modes interwork to facilitate activation and deactivation. in this case activation was initiated by an ar request at the terminal side and deactivation by a dr command at the lt side. activation could also be initialized at the lt side using an ar request. figure 8 example for octat-p activation and deactivation note: t1: < 250 m s time for error free level detection t2: < 10 ms time for synchronization t3: 2 ms time for error free detection of info 0 info 0 info 1w info 2 info 1 info 4 info 3 info 0 info 0 lt di uai -> ai dr t3 t2 ar t1
peb 2096 semiconductor group 16 05.98 4 registers description 4.1 identification register C (read) unchanged 4.2 general configuration register C (write) unchanged 4.3 bit error register C (read) address: 1 h format: initial value: 00 h description: beon = 1: bit error occurred on dasl compatible interface in ch. n code violation detected. the bit error register is reset after reading the register 4.4 configuration register for dasl compatible line interfaces C (write) address: 2 h format: initial value: 00 h if the mode pin is connected to v dd or 20 h if the mode pin is connected to v ss description: equdis : disables the equalizer when set to 1 4.5 test registers C (read/write) test registers are implemented in the address range of 8 h to a h ; they are not for customer use. bit 7 bit 0 beo7 beo6 beo5 beo4 beo3 beo2 beo1 beo0 bit 7 bit 0 00equdis0000 0
peb 2096 semiconductor group 17 05.98 4.6 mode register C (write) address: b h format: initial value: 00 h description: dasl 1 enables dasl compatible behavior bit 7 bit 0 dasl000000 0

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